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ISCA
2005
IEEE
147views Hardware» more  ISCA 2005»
15 years 11 months ago
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling
This paper examines the area, power, performance, and design issues for the on-chip interconnects on a chip multiprocessor, attempting to present a comprehensive view of a class o...
Rakesh Kumar, Victor V. Zyuban, Dean M. Tullsen
MICRO
1999
IEEE
98views Hardware» more  MICRO 1999»
15 years 9 months ago
Instruction Fetch Mechanisms for Multipath Execution Processors
Branch mispredictions can have a major performance impact on high-performance processors. Multipath execution has recently been introduced to help limit the misprediction penaltie...
Artur Klauser, Dirk Grunwald
152
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AMEC
2004
Springer
15 years 10 months ago
Designing Auctions for Deliberative Agents
Abstract. In many settings, bidding agents for auctions do not know their preferences a priori. Instead, they must actively determine them through deliberation (e.g., information p...
Kate Larson, Tuomas Sandholm
ICDCS
2012
IEEE
13 years 7 months ago
Scalable Name Lookup in NDN Using Effective Name Component Encoding
—Name-based route lookup is a key function for Named Data Networking (NDN). The NDN names are hierarchical and have variable and unbounded lengths, which are much longer than IPv...
Yi Wang, Keqiang He, Huichen Dai, Wei Meng, Junche...

Publication
509views
17 years 4 months ago
Some Issues in Auctions with Manipulative Players
Some Issues in Auctions with Manipulative Players
Aly Farag