Sciweavers

5623 search results - page 1051 / 1125
» Incremental Mechanism Design
Sort
View
92
Voted
MICRO
2006
IEEE
135views Hardware» more  MICRO 2006»
15 years 6 months ago
Support for High-Frequency Streaming in CMPs
As the industry moves toward larger-scale chip multiprocessors, the need to parallelize applications grows. High inter-thread communication delays, exacerbated by over-stressed hi...
Ram Rangan, Neil Vachharajani, Adam Stoler, Guilhe...
88
Voted
MICRO
2006
IEEE
84views Hardware» more  MICRO 2006»
15 years 6 months ago
Reunion: Complexity-Effective Multicore Redundancy
To protect processor logic from soft errors, multicore redundant architectures execute two copies of a program on separate cores of a chip multiprocessor (CMP). Maintaining identi...
Jared C. Smolens, Brian T. Gold, Babak Falsafi, Ja...
122
Voted
RTSS
2006
IEEE
15 years 6 months ago
MCGREP - A Predictable Architecture for Embedded Real-Time Systems
Real-time systems design involves many important choices, including that of the processor. The fastest processors achieve performance by utilizing architectural features that make...
Jack Whitham, Neil C. Audsley
ACISP
2006
Springer
15 years 6 months ago
Towards Provable Security for Ubiquitous Applications
Abstract. The emergence of computing environments where smart devices are embedded pervasively in the physical world has made possible many interesting applications and has trigger...
Mike Burmester, Tri Van Le, Breno de Medeiros
125
Voted
CF
2006
ACM
15 years 6 months ago
Dynamic thread assignment on heterogeneous multiprocessor architectures
In a multi-programmed computing environment, threads of execution exhibit different runtime characteristics and hardware resource requirements. Not only do the behaviors of distin...
Michela Becchi, Patrick Crowley
« Prev « First page 1051 / 1125 Last » Next »