Sciweavers

5623 search results - page 1075 / 1125
» Incremental Mechanism Design
Sort
View
84
Voted
ICCAD
2000
IEEE
95views Hardware» more  ICCAD 2000»
15 years 5 months ago
Test of Future System-on-Chips
Spurred by technology leading to the availability of millions of gates per chip, system-level integration is evolving as a new paradigm, allowing entire systems to be built on a s...
Yervant Zorian, Sujit Dey, Mike Rodgers
ISCA
2000
IEEE
99views Hardware» more  ISCA 2000»
15 years 4 months ago
Transient fault detection via simultaneous multithreading
Smaller feature sizes, reduced voltage levels, higher transistor counts, and reduced noise margins make future generations of microprocessors increasingly prone to transient hardw...
Steven K. Reinhardt, Shubhendu S. Mukherjee
MSS
2000
IEEE
160views Hardware» more  MSS 2000»
15 years 4 months ago
Implementation of a Fault-Tolerant Real-Time Network-Attached Storage Device
Phoenix is a fault-tolerantreal-time network-attachedstorage device (NASD). Like other NASD architectures, Phoenix provides an object-based interface to data stored on network-att...
Ashish Raniwala, Srikant Sharma, Anindya Neogi, Tz...
ASPLOS
2000
ACM
15 years 4 months ago
Architectural Support for Fast Symmetric-Key Cryptography
The emergence of the Internet as a trusted medium for commerce and communication has made cryptography an essential component of modern information systems. Cryptography provides ...
Jerome Burke, John McDonald, Todd M. Austin
114
Voted
PADS
1999
ACM
15 years 4 months ago
Shock Resistant Time Warp
In an attempt to cope with time-varying workload, traditional adaptive Time Warp protocols are designed to react in response to performance changes by altering control parameter c...
Alois Ferscha, James Johnson
« Prev « First page 1075 / 1125 Last » Next »