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» Incremental elaboration for run-time reconfigurable hardware...
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FPL
2005
Springer
140views Hardware» more  FPL 2005»
15 years 3 months ago
A Configuration Memory Architecture for Fast Run-Time-Reconfiguration of FPGAs
This paper presents a configuration memory architecture that offers fast FPGA reconfiguration. The underlying principle behind the design is the use of fine-grained partial rec...
Usama Malik, Oliver Diessel
ERSA
2006
197views Hardware» more  ERSA 2006»
14 years 11 months ago
A High Speed, Run Time Reconfigurable Image Acquisition processor for a Missile Approach Warning System
High frame rate video capture and image processing is an important capability for applications in defense and homeland security where incoming missiles must be detected in very sh...
Vinay Sriram, David Kearney
ESTIMEDIA
2003
Springer
15 years 2 months ago
Run-Time Scheduling for Multimedia Applications on Dynamically Reconfigurable Systems
Current multimedia applications are characterized by highly dynamic and non-deterministic behavior as well as high-performance requirements. In addition, portable devices demand a...
Javier Resano, Diederik Verkest, Daniel Mozos, Ser...
CC
2008
Springer
240views System Software» more  CC 2008»
14 years 11 months ago
Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs
JIT compilation is a model of execution which translates at run time critical parts of the program to a low level representation. Typically a JIT compiler produces machine code fro...
Etienne Bergeron, Marc Feeley, Jean-Pierre David
FPL
2008
Springer
175views Hardware» more  FPL 2008»
14 years 11 months ago
File system access from reconfigurable FPGA hardware processes in BORPH
This paper presents the design and implementation of BORPH's kernel file system layer that provides FPGA processes direct access to the general file system. Using a semantics...
Hayden Kwok-Hay So, Robert W. Brodersen