26 search results - page 3 / 6 » Incremental elaboration for run-time reconfigurable hardware... |
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Voted
DDECS
2008
IEEE
15 years 4 months ago
2008
IEEE
— Due to ever increasing design sizes more efficient tools for Automatic Test Pattern Generation (ATPG) are needed. Recently ATPG based on Boolean satisfiability (SAT) has been ...
ASAP
2007
IEEE
15 years 1 months ago
2007
IEEE
In this paper we present a novel adder/subtracter arithmetic unit that combines Binary and Binary Code Decimal (BCD) operations. The proposed unit uses effective addition/subtract...
IPPS
2006
IEEE
15 years 3 months ago
2006
IEEE
In reconfigurable systems, reconfiguration latency is a very important factor impact the system performance. In this paper, a framework is proposed that integrates the temporal pa...
DSD
2009
IEEE
15 years 4 months ago
2009
IEEE
—As CMOS process technology advances towards 32nm, SoC complexity continuously grows but its dependability significantly decreases. In this paper, a beamforming chip 1 is designe...
FPL
2000
Springer
15 years 1 months ago
2000
Springer
This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standa...