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» Incremental formal design verification
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ISSRE
2000
IEEE
15 years 2 months ago
Can Intuition Become Rigorous? Foundations for UML Model Verification Tools
The Unified Modeling Language, UML, is the objectoriented notation adopted as the standard for objectoriented Analysis and Design by the Object Management Group. This paper report...
José Luis Fernández Alemán, J...
ASYNC
2002
IEEE
120views Hardware» more  ASYNC 2002»
15 years 2 months ago
Relative Timing Based Verification of Timed Circuits and Systems
Advanced clock-delayed1 and self-resetting domino circuits are becoming increasingly important design styles in aggressive synchronous as well as asynchronous design. Their design...
Peter A. Beerel, Ken S. Stevens, Hoshik Kim
SIGSOFT
2005
ACM
15 years 10 months ago
Towards a unified formal model for supporting mechanisms of dynamic component update
The continuous requirements of evolving a delivered software system and the rising cost of shutting down a running software system are forcing researchers and practitioners to fin...
Junrong Shen, Xi Sun, Gang Huang, Wenpin Jiao, Yan...
DATE
1999
IEEE
134views Hardware» more  DATE 1999»
15 years 2 months ago
Verifying Imprecisely Working Arithmetic Circuits
If real number calculations are implemented as circuits, only a limited preciseness can be obtained. Hence, formal verification can not be used to prove the equivalence between th...
Michaela Huhn, Klaus Schneider, Thomas Kropf, Geor...
ISSS
2002
IEEE
125views Hardware» more  ISSS 2002»
15 years 2 months ago
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification
We have fabricated a Chip Multiprocessor prototype code-named Merlot to proof our novel speculative multithreading architecture. On Merlot, multiple threads provide wider issue wi...
Satoshi Matsushita