452 search results - page 35 / 91 » Incremental formal design verification |
65
Voted
DAC
2010
ACM
15 years 1 months ago
2010
ACM
Timing exception verification has become a center of interest as incorrect constraints can lead to chip failures. Proving that a false path is valid or not is a difficult problem ...
93
Voted
FMCAD
2008
Springer
14 years 11 months ago
2008
Springer
Post-silicon debug is the problem of determining what's wrong when the fabricated chip of a new design behaves incorrectly. This problem now consumes over half of the overall ...
FM
2009
Springer
14 years 7 months ago
2009
Springer
Abstract. This paper presents a Rewriting Logic framework that formalizes the interactions between Web servers and Web browsers through icating protocol abstracting HTTP. The propo...
FMCAD
2007
Springer
15 years 1 months ago
2007
Springer
Parameterized heuristics abound in computer aided design and verification, and manual tuning of the respective parameters is difficult and time-consuming. Very recent results from ...
93
Voted
WWW
2004
ACM
15 years 10 months ago
2004
ACM
Complex Semantic Web (SW) services may have intricate data state, autonomous process behavior and concurrent interactions. The design of such SW service systems requires precise a...