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» Incremental formal design verification
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ENTCS
2008
118views more  ENTCS 2008»
14 years 9 months ago
The STSLib Project: Towards a Formal Component Model Based on STS
We present the current state of our STSLib project. This project aims at defining an environment to formally specify and execute software components. One important feature is that...
Fabrício Fernandes, Jean-Claude Royer
ICST
2009
IEEE
14 years 7 months ago
Putting Formal Specifications under the Magnifying Glass: Model-based Testing for Validation
A software development process is conceptually an abstract form of model transformation, starting from an enduser model of requirements, through to a system model for which code c...
Emine G. Aydal, Richard F. Paige, Mark Utting, Jim...
DAC
2007
ACM
15 years 10 months ago
An Effective Guidance Strategy for Abstraction-Guided Simulation
tive Guidance Strategy for Abstraction-Guided Simulation Flavio M. De Paula Alan J. Hu Department of Computer Science, University of British Columbia, {depaulfm, ajh}@cs.ubc.ca D...
Flavio M. de Paula, Alan J. Hu
MEMOCODE
2010
IEEE
14 years 7 months ago
Proving transaction and system-level properties of untimed SystemC TLM designs
Electronic System Level (ESL) design manages the complexity of todays systems by using abstract models. In this context Transaction Level Modeling (TLM) is state-of-theart for desc...
Daniel Große, Hoang M. Le, Rolf Drechsler
BELL
2000
107views more  BELL 2000»
14 years 9 months ago
Automating software feature verification
A significant part of the call processing software for Lucent's new PathStar access server [FSW98] was checked with automated formal verification techniques. The verification...
Gerard J. Holzmann, Margaret H. Smith