Sciweavers

452 search results - page 39 / 91
» Incremental formal design verification
Sort
View
FMCAD
2008
Springer
14 years 11 months ago
Recording Synthesis History for Sequential Verification
Performing synthesis and verification in isolation has two undesirable consequences: (1) verification runs the risk of becoming intractable, and (2) strong sequential optimization...
Alan Mishchenko, Robert K. Brayton
UML
2004
Springer
15 years 3 months ago
System-on-Chip Verification Process Using UML
Abstract. In this paper, we propose a verification methodology for System-OnChip (SoC) design using Unified Modeling Language (UML). We introduce UML as a formal model to analyze a...
Qiang Zhu, Tsuneo Nakata, Masataka Mine, Kenichiro...
ICFEM
2010
Springer
14 years 8 months ago
Model-Driven Protocol Design Based on Component Oriented Modeling
Abstract. Due to new emerging areas in the communication field there is a constant need for the design of novel communication protocols. This demands techniques for a rapid and eff...
Prabhu Shankar Kaliappan, Hartmut König, Seba...
PLDI
1997
ACM
15 years 1 months ago
Incremental Analysis of real Programming Languages
A major research goal for compilers and environments is the automatic derivation of tools from formal specifications. However, the formal model of the language is often inadequat...
Tim A. Wagner, Susan L. Graham
RSP
2003
IEEE
169views Control Systems» more  RSP 2003»
15 years 3 months ago
Rapid Prototyping and Incremental Evolution Using SLAM
The paper shows the outlines of the SLAM system and how its design is suitable for automating rapid prototyping. The system includes a very expressive object oriented specificati...
Ángel Herranz-Nieva, Juan José Moren...