Sciweavers

452 search results - page 47 / 91
» Incremental formal design verification
Sort
View
SIGSOFT
2007
ACM
15 years 10 months ago
SLEDE: lightweight verification of sensor network security protocol implementations
Finding flaws in security protocol implementations is hard. Finding flaws in the implementations of sensor network security protocols is even harder because they are designed to p...
Youssef Hanna
ACSD
2001
IEEE
74views Hardware» more  ACSD 2001»
15 years 1 months ago
From Code to Models
One of the corner stones of formal methods is the notion traction enables analysis. By the construction of act model we can trade implementation detail for analytical power. The i...
Gerard J. Holzmann
IFM
2000
Springer
15 years 1 months ago
ISpec: Towards Practical and Sound Interface Specifications
Abstract. This paper introduces the ISpec approach to interface specification. ISpec supports the development of interface specifications at various levels of formality and detail ...
H. B. M. Jonkers
DAC
2003
ACM
15 years 10 months ago
Automatic trace analysis for logic of constraints
Verification of system designs continues to be a major challenge today. Simulation remains the primary tool for making sure that implementations perform as they should. We present...
Xi Chen, Harry Hsieh, Felice Balarin, Yosinori Wat...
VLSID
2002
IEEE
177views VLSI» more  VLSID 2002»
15 years 10 months ago
RTL-Datapath Verification using Integer Linear Programming
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most...
Raik Brinkmann, Rolf Drechsler