452 search results - page 48 / 91 » Incremental formal design verification |
VSTTE
2010
Springer
14 years 7 months ago
2010
Springer
A suite of verification benchmarks for software verification tools and techniques, presented at VSTTE 2008 [11], provides an initial catalogue of benchmark challenges for the Verif...
ACSC
2004
IEEE
15 years 1 months ago
2004
IEEE
An approach to system verification is described in which design artefacts produced during forward engineering are automatically compared to corresponding artefacts produced during...
SIGSOFT
2003
ACM
15 years 10 months ago
2003
ACM
State machine based formalisms such as labelled transition systems (LTS) are generally assumed to be complete descriptions m behaviour at some level of abstraction: if a labelled ...
CBSE
2011
Springer
13 years 9 months ago
2011
Springer
Software components are increasingly assembled from other components. Each component may further depend on others, and each may have multiple active versions. The total number of ...
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CADE
2008
Springer
15 years 10 months ago
2008
Springer
Many safety- and security-critical systems are real-time systems and, as a result, tools and techniques for verifying real-time systems are extremely important. Simulation and test...