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» Incremental formal design verification
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JUCS
2010
152views more  JUCS 2010»
14 years 4 months ago
Verification of Structural Pattern Conformance Using Logic Programming
: This paper formalizes UML class diagrams and structural patterns as mathematical objects and provides a precise notion of conformance of a structural model specified as a class d...
Lunjin Lu, Dae-Kyoo Kim, Yuanlin Zhu, Sangsig Kim
EJC
2008
14 years 11 months ago
Center Fragments for Upscaling and Verification in Database Semantics
The notion of a fragment was coined by Montague 1974 to illustrate the formal handling of certain puzzles, such as de dicto/de re, in a truth-conditional semantics for natural lan...
Roland Hausser
DAC
2003
ACM
15 years 10 months ago
A hybrid SAT-based decision procedure for separation logic with uninterpreted functions
SAT-based decision procedures for quantifier-free fragments of firstorder logic have proved to be useful in formal verification. These decision procedures are either based on enco...
Sanjit A. Seshia, Shuvendu K. Lahiri, Randal E. Br...
CAV
2009
Springer
176views Hardware» more  CAV 2009»
15 years 10 months ago
PAT: Towards Flexible Verification under Fairness
Recent development on distributed systems has shown that a variety of fairness constraints (some of which are only recently defined) play vital roles in designing self-stabilizing ...
Jun Sun 0001, Yang Liu 0003, Jin Song Dong, Jun Pa...
VLSID
2001
IEEE
129views VLSI» more  VLSID 2001»
15 years 10 months ago
Design Of Provably Correct Storage Arrays
In this paper we describe a hardware design method for memory and register arrays that allows the application of formal equivalence checking for comparing a high-level register tr...
Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann