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» Incremental formal design verification
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CODES
2008
IEEE
14 years 11 months ago
Model checking SystemC designs using timed automata
SystemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify SystemC designs. In...
Paula Herber, Joachim Fellmuth, Sabine Glesner
GLVLSI
2008
IEEE
150views VLSI» more  GLVLSI 2008»
14 years 10 months ago
Using unsatisfiable cores to debug multiple design errors
Due to the increasing complexity of today's circuits a high degree of automation in the design process is mandatory. The detection of faults and design errors is supported qu...
André Sülflow, Görschwin Fey, Rod...
SOFSEM
2007
Springer
15 years 3 months ago
Separation of Concerns and Consistent Integration in Requirements Modelling
Due to their increasing complexity, design of software systems is not becoming easier. Furthermore, modern applications ranging from enterprise to embedded systems require very hig...
Xin Chen, Zhiming Liu, Vladimir Mencl
SIGSOFT
2009
ACM
15 years 10 months ago
Probabilistic environments in the quantitative analysis of (non-probabilistic) behaviour models
System specifications have long been expressed through automata-based languages, enabling verification techniques such as model checking. These verification techniques can assess ...
Esteban Pavese, Sebastián Uchitel, Ví...
PDSE
1998
126views more  PDSE 1998»
14 years 11 months ago
Validation and Test Generation for Object-Oriented Distributed Software
The development of correct OO distributed software is a daunting task as soon as the distributed interactions are not trivial. This is due to the inherent complexity of distribute...
Thierry Jéron, Jean-Marc Jézé...