452 search results - page 52 / 91 » Incremental formal design verification |
ECBS
2010
IEEE
15 years 3 months ago
2010
IEEE
Abstract—Many design steps during system development like functional partitioning, refactoring of the architecture, or the mapping to the platform - can be understood as an explo...
101
click to vote
FDL
2007
IEEE
15 years 4 months ago
2007
IEEE
SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...
ICSE
2004
IEEE-ACM
15 years 3 months ago
2004
IEEE-ACM
Prior research attempts to formalize the structure of object-oriented design patterns for a more precise specification of design patterns. It also allows automation support to be ...
CHARME
2003
Springer
15 years 1 months ago
2003
Springer
Industrial verification teams are actively developing suitable event sequence languages for hardware verification. Such languages must be expressive, designer friendly, and hardwar...
APSEC
2004
IEEE
15 years 1 months ago
2004
IEEE
To formalize a software process, its important aspects must be extracted as a model. Many processes are used repeatedly, and the ability to automate a process is also desired. One...