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» Incremental formal design verification
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ICSE
2000
IEEE-ACM
15 years 1 months ago
Verification of time partitioning in the DEOS scheduler kernel
This paper describes an experiment to use the Spin model checking system to support automated verification of time partitioning in the Honeywell DEOS real-time scheduling kernel. ...
John Penix, Willem Visser, Eric Engstrom, Aaron La...
CORR
2010
Springer
59views Education» more  CORR 2010»
14 years 8 months ago
Refinement and Verification of Real-Time Systems
This paper discusses highly general mechanisms for specifying the refinement of a real-time system as a collection of lower level parallel components that preserve the timing and ...
Paul Z. Kolano, Carlo A. Furia, Richard A. Kemmere...
KBS
2007
74views more  KBS 2007»
14 years 9 months ago
GUIDE: Games with UML for interactive design exploration
In this paper we present our design tool GUIDE, which allows the user to explore a design in UML interactively by playing a game. The game incorporates both the design model and a...
Jennifer Tenzer, Perdita Stevens
CORR
2008
Springer
143views Education» more  CORR 2008»
14 years 9 months ago
A Type System for Data-Flow Integrity on Windows Vista
The Windows Vista operating system implements an interesting model of multi-level integrity. We observe that in this model, trusted code must participate in any information-flow a...
Avik Chaudhuri, Prasad Naldurg, Sriram K. Rajamani
ACSD
2006
IEEE
109views Hardware» more  ACSD 2006»
14 years 11 months ago
Synthesis of Synchronous Interfaces
Reuse of IP blocks has been advocated as a means to conquer the complexity of today's system-on-chip (SoC) designs. Component integration and verification in such systems is ...
Purandar Bhaduri, S. Ramesh