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» Incremental formal design verification
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POPL
2010
ACM
15 years 7 months ago
From Program Verification to Program Synthesis
This paper describes a novel technique for the synthesis of imperative programs. Automated program synthesis has the potential to make programming and the design of systems easier...
Saurabh Srivastava, Sumit Gulwani, Jeffrey S. Fost...
EPK
2006
114views Management» more  EPK 2006»
14 years 11 months ago
Verifying Properties of (Timed) Event Driven Process Chains by Transformation to Hybrid Automata
Abstract: Event-driven Process Chains (EPCs) are a commonly used modelling technique for design and documentation of business processes. Although EPCs have an easy-to-understand no...
Stefan Denne
SP
2010
IEEE
152views Security Privacy» more  SP 2010»
14 years 7 months ago
Scalable Parametric Verification of Secure Systems: How to Verify Reference Monitors without Worrying about Data Structure Size
The security of systems such as operating systems, hypervisors, and web browsers depend critically on reference monitors to correctly enforce their desired security policy in the ...
Jason Franklin, Sagar Chaki, Anupam Datta, Arvind ...
ATAL
2008
Springer
14 years 11 months ago
Checking correctness of business contracts via commitments
Business contracts tend to be complex. In current practice, contracts are often designed by hand and adopted by their participants after, at best, a manual analysis. This paper mo...
Nirmit Desai, Nanjangud C. Narendra, Munindar P. S...
SIMUTOOLS
2008
14 years 11 months ago
Transforming sources to petri nets: a way to analyze execution of parallel programs
Model checking is a suitable formal technique to analyze parallel programs' execution in an industrial context because automated tools can be designed and operated with very ...
Jean-Baptiste Voron, Fabrice Kordon