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» Incremental formal design verification
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FDL
2004
IEEE
15 years 1 months ago
A Formal Verification Approach for IP-based Designs
This paper proposes a formal verification methodology which is smoothly integrated with component-based system-level design, using a divide and conquer approach. The methodology a...
Daniel Karlsson, Petru Eles, Zebo Peng
TELSYS
2002
126views more  TELSYS 2002»
14 years 9 months ago
Framework and Tool Support for Formal Verification of Highspeed Transfer Protocol Designs
Formal description techniques, verification methods, and their tool-based automated application meanwhile provide valuable support for the formal analysis of communication protocol...
Peter Herrmann, Heiko Krumm, Olaf Drögehorn, ...
HASE
2008
IEEE
14 years 9 months ago
Aiding Modular Design and Verification of Safety-Critical Time-Triggered Systems by Use of Executable Formal Specifications
Designing safety-critical systems is a complex process, and especially when the design is carried out at different f abstraction where the correctness of the design at one level i...
Kohei Sakurai, Péter Bokor, Neeraj Suri
FMCAD
2009
Springer
15 years 4 months ago
Formal verification of analog designs using MetiTarski
William Denman, Behzad Akbarpour, Sofiène T...
CAV
2004
Springer
111views Hardware» more  CAV 2004»
15 years 3 months ago
Using Interface Refinement to Integrate Formal Verification into the Design Cycle
Jacob Chang, Sergey Berezin, David L. Dill