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PPOPP
2010
ACM
16 years 1 months ago
Data transformations enabling loop vectorization on multithreaded data parallel architectures
Loop vectorization, a key feature exploited to obtain high performance on Single Instruction Multiple Data (SIMD) vector architectures, is significantly hindered by irregular memo...
Byunghyun Jang, Perhaad Mistry, Dana Schaa, Rodrig...
SDM
2009
SIAM
220views Data Mining» more  SDM 2009»
16 years 1 months ago
Bayesian Cluster Ensembles.
Cluster ensembles provide a framework for combining multiple base clusterings of a dataset to generate a stable and robust consensus clustering. There are important variants of th...
Hongjun Wang, Hanhuai Shan, Arindam Banerjee
ICCAD
2007
IEEE
92views Hardware» more  ICCAD 2007»
16 years 1 months ago
Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays
Several technologies with sub-lithographic features are targeting the fabrication of crossbar memories in which the nanowire decoder is playing a major role. In this paper, we sug...
M. Haykel Ben Jamaa, Kirsten E. Moselund, David At...
ICCAD
2006
IEEE
119views Hardware» more  ICCAD 2006»
16 years 1 months ago
Energy management for real-time embedded systems with reliability requirements
With the continued scaling of CMOS technologies and reduced design margins, the reliability concerns induced by transient faults have become prominent. Moreover, the popular energ...
Dakai Zhu, Hakan Aydin
ICCAD
2005
IEEE
176views Hardware» more  ICCAD 2005»
16 years 1 months ago
Statistical gate sizing for timing yield optimization
— Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely...
Debjit Sinha, Narendra V. Shenoy, Hai Zhou
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