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DAC
2010
ACM
15 years 3 months ago
Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms
We present a methodology for off-chip memory bandwidth minimization through application-driven L2 cache partitioning in multicore systems. A major challenge with multi-core system...
Chenjie Yu, Peter Petrov
ISCA
2000
IEEE
156views Hardware» more  ISCA 2000»
15 years 4 months ago
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Reconfigurable hardware has the potential for significant performance improvements by providing support for application−specific operations. We report our experience with Chimae...
Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithv...
KDD
2004
ACM
117views Data Mining» more  KDD 2004»
16 years 5 days ago
Predicting customer shopping lists from point-of-sale purchase data
This paper describes a prototype that predicts the shopping lists for customers in a retail store. The shopping list prediction is one aspect of a larger system we have developed ...
Chad M. Cumby, Andrew E. Fano, Rayid Ghani, Marko ...
CLOUD
2010
ACM
15 years 4 months ago
Stateful bulk processing for incremental analytics
This work addresses the need for stateful dataflow programs that can rapidly sift through huge, evolving data sets. These data-intensive applications perform complex multi-step c...
Dionysios Logothetis, Christopher Olston, Benjamin...
BMCBI
2005
108views more  BMCBI 2005»
14 years 11 months ago
Storing, linking, and mining microarray databases using SRS
Background: SRS (Sequence Retrieval System) has proven to be a valuable platform for storing, linking, and querying biological databases. Due to the availability of a broad range ...
Antoine Veldhoven, Don de Lange, Marcel Smid, Vict...