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ICCAD
2006
IEEE
124views Hardware» more  ICCAD 2006»
15 years 8 months ago
Robust system level design with analog platforms
An approach to robust system level mixed signal design is presented based on analog platforms. The bottom-up characterization phase of platform components provides accurate perfor...
Fernando De Bernardinis, Pierluigi Nuzzo, Alberto ...
HPCA
2000
IEEE
15 years 4 months ago
Impact of Chip-Level Integration on Performance of OLTP Workloads
With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. So...
Luiz André Barroso, Kourosh Gharachorloo, A...
TITS
2010
117views Education» more  TITS 2010»
14 years 6 months ago
Lane-Level Integrity Provision for Navigation and Map Matching With GNSS, Dead Reckoning, and Enhanced Maps
Lane-level positioning and map matching are some of the biggest challenges for navigation systems. Additionally, in safety applications or in those with critical performance requir...
Rafael Toledo-Moreo, David Bétaille, Fran&c...
GECCO
2004
Springer
136views Optimization» more  GECCO 2004»
15 years 5 months ago
System Level Hardware-Software Design Exploration with XCS
Abstract. The current trend in Embedded Systems (ES) design is moving towards the integration of increasingly complex applications on a single chip. An Embedded System has to satis...
Fabrizio Ferrandi, Pier Luca Lanzi, Donatella Sciu...
ICAC
2007
IEEE
15 years 6 months ago
SLA Decomposition: Translating Service Level Objectives to System Level Thresholds
In today’s complex and highly dynamic computing environments, systems/services have to be constantly adjusted to meet Service Level Agreements (SLAs) and to improve resource uti...
Yuan Chen, Subu Iyer, Xue Liu, Dejan S. Milojicic,...