66 search results - page 4 / 14 » Informed operators: Speeding up genetic-algorithm-based desi... |
ASPDAC
2001
ACM
13 years 10 months ago
2001
ACM
Our earlier work for fast evaluation of power consumption of general cores in a system-on-a-chip described techniques that involved isolating high-level instructions of a core, me...
CGO
2007
IEEE
14 years 19 days ago
2007
IEEE
The demand for high performance has driven acyclic computation accelerators into extensive use in modern embedded and desktop architectures. Accelerators that are ideal from a sof...
DAC
2005
ACM
14 years 7 months ago
2005
ACM
Dynamic voltage scaling (DVS) is a well-known low power design technique that reduces the processor energy by slowing down the DVS processor and stretching the task execution time...
CIKM
2009
Springer
13 years 11 months ago
2009
Springer
Solid State Drive (SSD), emerging as new data storage media with high random read speed, has been widely used in laptops, desktops, and data servers to replace hard disk during th...
EURODAC
1994
IEEE
13 years 10 months ago
1994
IEEE
In performance-driven interconnect design, delay estimators are used to determine both the topology and the layout of good routing trees. We address the class of moment-matching, ...