Sciweavers

550 search results - page 107 / 110
» Inherently Parallel Geometric Computations
Sort
View
103
Voted
HPCA
2008
IEEE
15 years 10 months ago
Regional congestion awareness for load balance in networks-on-chip
Interconnection networks-on-chip (NOCs) are rapidly replacing other forms of interconnect in chip multiprocessors and system-on-chip designs. Existing interconnection networks use...
Paul Gratz, Boris Grot, Stephen W. Keckler
112
Voted
ICDCSW
2009
IEEE
15 years 4 months ago
Embedded Virtual Machines for Robust Wireless Control Systems
Embedded wireless networks have largely focused on openloop sensing and monitoring. To address actuation in closedloop wireless control systems there is a strong need to re-think ...
Rahul Mangharam, Miroslav Pajic
CF
2009
ACM
15 years 4 months ago
Mapping the LU decomposition on a many-core architecture: challenges and solutions
Recently, multi-core architectures with alternative memory subsystem designs have emerged. Instead of using hardwaremanaged cache hierarchies, they employ software-managed embedde...
Ioannis E. Venetis, Guang R. Gao
104
Voted
NDSS
2008
IEEE
15 years 4 months ago
Automatic Protocol Format Reverse Engineering through Context-Aware Monitored Execution
Protocol reverse engineering has often been a manual process that is considered time-consuming, tedious and error-prone. To address this limitation, a number of solutions have rec...
Zhiqiang Lin, Xuxian Jiang, Dongyan Xu, Xiangyu Zh...
ANCS
2007
ACM
15 years 2 months ago
Ruler: high-speed packet matching and rewriting on NPUs
Programming specialized network processors (NPU) is inherently difficult. Unlike mainstream processors where architectural features such as out-of-order execution and caches hide ...
Tomas Hruby, Kees van Reeuwijk, Herbert Bos