Sciweavers

228 search results - page 10 / 46
» Input Output Characteristics of Scalable Parallel Applicatio...
Sort
View
DATE
2004
IEEE
154views Hardware» more  DATE 2004»
15 years 5 months ago
MultiNoC: A Multiprocessing System Enabled by a Network on Chip
The MultiNoC system implements a programmable onchip multiprocessing platform built on top of an efficient, low area overhead intra-chip interconnection scheme. The employed inter...
Aline Mello, Leandro Möller, Ney Calazans, Fe...
ICDCS
2002
IEEE
15 years 6 months ago
An Extensible and Scalable Content Adaptation Pipeline Architecture to Support Heterogeneous Clients
The importance of middleware and content adaptation has previously been demonstrated for pervasive use of Web-based applications. In this paper we propose a modular, extensible, a...
Thomas Phan, George Zorpas, Rajive Bagrodia
JAL
2008
89views more  JAL 2008»
15 years 1 months ago
Experimenting with parallelism for the instantiation of ASP programs
Abstract. In the last few years, the microprocessors technologies have been definitely moving to multi-core architectures, in order to improve performances as well as reduce power ...
Francesco Calimeri, Simona Perri, Francesco Ricca
EUROPAR
2009
Springer
15 years 5 months ago
A Buffer Space Optimal Solution for Re-establishing the Packet Order in a MPSoC Network Processor
We consider a multi-processor system-on-chip destined for streaming applications. An application is composed of one input and one output queue and in-between, several levels of ide...
Daniela Genius, Alix Munier Kordon, Khouloud Zine ...
DSD
2006
IEEE
73views Hardware» more  DSD 2006»
15 years 7 months ago
Flexible Two-Level Boolean Minimizer BOOM-II and Its Applications
We propose a novel two-level Boolean minimizer coming in succession to our previously developed minimizer BOOM, so we have named it BOOM-II. It is a combination of two minimizers,...
Petr Fiser, Hana Kubatova