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EURODAC
1995
IEEE
126views VHDL» more  EURODAC 1995»
15 years 1 months ago
Towards verifying VHDL descriptions of processors
We present a system for the formal veri cation of processors which combines a computer algebra simpli cation tool with an object-oriented approach. It has been successfully used f...
Laurent Arditi, Hélène Collavizza
EUROMICRO
1999
IEEE
15 years 2 months ago
Software Synthesis for System Level Design Using Process Execution Trees
Software synthesis for system level design languages becomes feasible because the current technology, pricing and application trends will most likely alleviate the industrial empha...
Leo J. van Bokhoven, Jeroen Voeten, Marc Geilen
ANSS
2003
IEEE
15 years 3 months ago
Internode: Internal Node Logic Computational Model
In this work, we present a computational behavioral model for logic gates called Internode (Internal Node Logic Computational Model) that considers the functionality of the gate a...
Alejandro Millán, Manuel J. Bellido, Jorge ...
SMILE
1998
Springer
15 years 2 months ago
Interactive 3D Modeling from Multiple Images Using Scene Regularities
Abstract. We present some recent progress in designing and implementing two interactive image-based 3D modeling systems. The first system constructs 3D models from a collection of ...
Heung-Yeung Shum, Richard Szeliski, Simon Baker, M...
COMPGEOM
2008
ACM
14 years 11 months ago
Visualizing and exploring planar algebraic arrangements: a web application
A web application is presented to compute, plot, and interactively explore planar arrangements induced by algebraic plane curves of arbitrary degree. It produces accurate curve pl...
Pavel Emeliyanenko, Michael Kerber