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DATE
2009
IEEE
189views Hardware» more  DATE 2009»
15 years 4 months ago
CUFFS: An instruction count based architectural framework for security of MPSoCs
—Multiprocessor System on Chip (MPSoC) architecture is rapidly gaining momentum for modern embedded devices. The vulnerabilities in software on MPSoCs are often exploited to caus...
Krutartha Patel, Sri Parameswaran, Roshan G. Ragel
ISHPC
2000
Springer
15 years 1 months ago
Limits of Task-Based Parallelism in Irregular Applications
Traditional parallel compilers do not effectively parallelize irregular applications because they contain little looplevel parallelism due to ambiguous memory references. We explo...
Barbara Kreaseck, Dean M. Tullsen, Brad Calder
ECRTS
2005
IEEE
15 years 3 months ago
Cache Contents Selection for Statically-Locked Instruction Caches: An Algorithm Comparison
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...
Antonio Martí Campoy, Isabelle Puaut, Angel...
CORR
2010
Springer
119views Education» more  CORR 2010»
14 years 7 months ago
Using Information Theory to Study the Efficiency and Capacity of Computers and Similar Devices
We address the problems of estimating the computer efficiency and the computer capacity. We define the computer efficiency and capacity and suggest a method for their estimation, ...
Boris Ryabko
CF
2004
ACM
15 years 3 months ago
A first glance at Kilo-instruction based multiprocessors
The ever increasing gap between processor and memory speed, sometimes referred to as the Memory Wall problem [42], has a very negative impact on performance. This mismatch will be...
Marco Galluzzi, Valentin Puente, Adrián Cri...