174 search results - page 11 / 35 » Instruction Fetch Mechanisms for Multipath Execution Process... |
HPCA
2006
IEEE
15 years 10 months ago
2006
IEEE
Building processors with large instruction windows has been proposed as a mechanism for overcoming the memory wall, but finding a feasible and implementable design has been an elu...
ICCD
2006
IEEE
15 years 6 months ago
2006
IEEE
—Current micro-architecture blindly uses the address in the program counter to fetch and execute instructions without validating its legitimacy. Whenever this blind-folded instru...
HPCA
2008
IEEE
15 years 10 months ago
2008
IEEE
In this paper, we propose Runahead Threads (RaT) as a valuable solution for both reducing resource contention and exploiting memory-level parallelism in Simultaneous Multithreaded...
CC
2000
Springer
14 years 9 months ago
2000
Springer
The performance of a Java Virtual Machine (JVM) interpreter running on a very long instruction word (VLIW) processor can be improved by means of pipelining. While one bytecode is i...
SAMOS
2007
Springer
15 years 3 months ago
2007
Springer
Abstract—Most research work on (Simultaneous Multithreading Processors) SMTs focuses on improving throughput and/or fairness, or on prioritizing some threads over others in a wor...