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MICRO
2002
IEEE
97views Hardware» more  MICRO 2002»
15 years 2 months ago
Three extensions to register integration
Register integration (or just integration) is a register renaming discipline that implements instruction reuse via physical register sharing. Initially developed to perform squash...
Vlad Petric, Anne Bracy, Amir Roth
CCS
2003
ACM
15 years 2 months ago
Countering code-injection attacks with instruction-set randomization
We describe a new, general approach for safeguarding systems against any type of code-injection attack. We apply Kerckhoff’s principle, by creating process-specific randomized ...
Gaurav S. Kc, Angelos D. Keromytis, Vassilis Preve...
ISCA
2006
IEEE
144views Hardware» more  ISCA 2006»
14 years 9 months ago
Conditional Memory Ordering
Conventional relaxed memory ordering techniques follow a proactive model: at a synchronization point, a processor makes its own updates to memory available to other processors by ...
Christoph von Praun, Harold W. Cain, Jong-Deok Cho...
IISWC
2008
IEEE
15 years 4 months ago
Energy-aware application scheduling on a heterogeneous multi-core system
Heterogeneous multi-core processors are attractive for power efficient computing because of their ability to meet varied resource requirements of diverse applications in a workloa...
Jian Chen, Lizy Kurian John
TCAD
2008
101views more  TCAD 2008»
14 years 9 months ago
Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors
Functional correctness is a vital attribute of any hardware design. Unfortunately, due to extremely complex architectures, widespread components, such as microprocessors, are often...
Ilya Wagner, Valeria Bertacco, Todd M. Austin