174 search results - page 33 / 35 » Instruction Fetch Mechanisms for Multipath Execution Process... |
ICPP
2008
IEEE
15 years 4 months ago
2008
IEEE
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
DAC
2005
ACM
14 years 11 months ago
2005
ACM
In this paper we present the impact of dynamically translating any sequence of instructions into combinational logic. The proposed approach combines a reconfigurable architecture ...
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ACSAC
2005
IEEE
15 years 3 months ago
2005
IEEE
Microscopic analysis of malicious code (malware) requires the aid of a variety of powerful tools. Chief among them is a debugger that enables runtime binary analysis at an instruc...
IEEEPACT
2006
IEEE
15 years 3 months ago
2006
IEEE
Modern out-of-order processors with non-blocking caches exploit Memory-Level Parallelism (MLP) by overlapping cache misses in a wide instruction window. The exploitation of MLP, h...
ASAP
2007
IEEE
15 years 1 months ago
2007
IEEE
Software-based, fine-grain control flow integrity (CFI) validation technique has been proposed to enforce control flow integrity of program execution. By validating every indirect...