1192 search results - page 103 / 239 » Instruction Level Distributed Processing |
COOP
2004
15 years 4 days ago
2004
This paper proposes a method which assists the firms for cooperating in make-to-order production. We especially focus on the operational decision levels of manufacturing companies ...
DAC
2004
ACM
15 years 11 months ago
2004
ACM
As process technology migrates to deep submicron with feature size less than 100nm, global wire delay is becoming a major hindrance in keeping the latency of intra-chip communicat...
DAC
2006
ACM
15 years 11 months ago
2006
ACM
Correctness is a paramount attribute of any microprocessor design; however, without novel technologies to tame the increasing complexity of design verification, the amount of bugs...
EGH
2005
Springer
15 years 4 months ago
2005
Springer
Complex shaders must be partitioned into multiple passes to execute on GPUs with limited hardware resources. Automatic partitioning gives rise to an NP-hard scheduling problem tha...
104
click to vote
CC
2003
Springer
15 years 4 months ago
2003
Springer
Abstract. The register allocation in loops is generally performed after or during the software pipelining process. This is because doing a conventional register allocation at firs...