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» Instruction Level Distributed Processing
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CCGRID
2006
IEEE
15 years 4 months ago
Proposal of MPI Operation Level Checkpoint/Rollback and One Implementation
With the increasing number of processors in modern HPC(High Performance Computing) systems, there are two emergent problems to solve. One is scalability, the other is fault tolera...
Yuan Tang, Graham E. Fagg, Jack Dongarra
EUROPAR
1999
Springer
15 years 2 months ago
Multi-stage Cascaded Prediction
Two-level predictors deliver highly accurate conditional branch prediction, indirect branch target prediction and value prediction. Accurate prediction enables speculative executio...
Karel Driesen, Urs Hölzle
ICPADS
1998
IEEE
15 years 2 months ago
A Dualthreaded Java Processor for Java Multithreading
Java-Web Computing paradigm changed Internet into computing environment. For Java-Web Computing and many Java applications, a new Java processor, called simultaneous multithreaded...
Chun-Mok Chung, Shin-Dug Kim
HPCA
2006
IEEE
15 years 10 months ago
Software-hardware cooperative memory disambiguation
In high-end processors, increasing the number of in-flight instructions can improve performance by overlapping useful processing with long-latency accesses to the main memory. Buf...
Ruke Huang, Alok Garg, Michael C. Huang
PC
2000
120views Management» more  PC 2000»
14 years 9 months ago
Real-time sonar beamforming on high-performance distributed computers
Rapid advancements in acoustical beamforming techniques for array signal processing are producing algorithms with increased levels of computational complexity. Concomitantly, auto...
Alan D. George, Jeff Markwell, Ryan Fogarty