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ICS
1995
Tsinghua U.
15 years 1 months ago
Optimum Modulo Schedules for Minimum Register Requirements
Modulo scheduling is an e cient technique for exploiting instruction level parallelism in a variety of loops, resulting in high performance code but increased register requirement...
Alexandre E. Eichenberger, Edward S. Davidson, San...
VLSID
2001
IEEE
144views VLSI» more  VLSID 2001»
15 years 10 months ago
Next Generation Network Processors
Networking hardware manufacturers face the dual demands of supporting ever increasing bandwidth requirements, while also delivering new features, such as the ability to implement ...
Deepak Kataria
COORDINATION
2006
Springer
15 years 1 months ago
Synthesizing Concurrency Control Components from Process Algebraic Specifications
Process algebraic specifications can provide useful support for the architectural design of software systems due to the possibility of analyzing their properties. In addition to th...
Edoardo Bontà, Marco Bernardo, Jeff Magee, ...
EUROPAR
2001
Springer
15 years 2 months ago
A Software Architecture for User Transparent Parallel Image Processing on MIMD Computers
Abstract. This paper describes a software architecture that allows image processing researchers to develop parallel applications in a transparent manner. The architecture’s main ...
Frank J. Seinstra, Dennis Koelma, Jan-Mark Geusebr...
RTAS
1999
IEEE
15 years 2 months ago
User Level Scheduling of Communicating Real-Time Tasks
Unique challenges are present when one tries to build distributed real-time applications using standard o -the-shelf systems which are in common use but are not necessarily design...
Chia Shen, Oscar González, Krithi Ramamrith...