1192 search results - page 62 / 239 » Instruction Level Distributed Processing |
SP
2005
IEEE
15 years 3 months ago
2005
IEEE
In this paper, we propose BIND (Binding Instructions aNd Data),1 a fine-grained attestation service for securing distributed systems. Code attestation has recently received consi...
ICPP
2008
IEEE
15 years 4 months ago
2008
IEEE
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
94
Voted
SOSP
1997
ACM
14 years 11 months ago
1997
ACM
Despite a large research effort, software distributed shared memory systems have not been widely used to run parallel applications across clusters of computers. The higher perform...
EUROPAR
2009
Springer
15 years 4 months ago
2009
Springer
An upgrade from dual-core to quad-core AMD processor on the Cray XT system at the Oak Ridge National Laboratory (ORNL) Leadership Computing Facility (LCF) has resulted in significa...
ICPP
2006
IEEE
15 years 4 months ago
2006
IEEE
We propose a series of aggressive register deallocation mechanisms to reduce the register file pressure and increase the parallelism exploited by superscalar microprocessors. Our ...