1192 search results - page 86 / 239 » Instruction Level Distributed Processing |
ICASSP
2008
IEEE
15 years 4 months ago
2008
IEEE
We address the design and optimization of an energy-efficient lifting-based 2D transform for wireless sensor networks with irregular spatial sampling. The 2D transform is designe...
111
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DAC
2007
ACM
15 years 11 months ago
2007
ACM
Mapping packet processing applications onto embedded network processors (NP) is a challenging task due to the unique constraints of NP systems and the characteristics of network a...
98
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HPCN
1998
Springer
15 years 2 months ago
1998
Springer
We describe the Paraflow system for connecting heterogeneous computing services together into a flexible and efficient data-mining metacomputer. There are three levels of parallel...
77
Voted
IPPS
2006
IEEE
15 years 4 months ago
2006
IEEE
With the advent of chip-multiprocessors (CMPs), Thread-Level Speculation (TLS) remains a promising technique for exploiting this highly multithreaded hardware to improve the perfo...
87
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IEEEPACT
2000
IEEE
15 years 2 months ago
2000
IEEE
Modern computers have taken advantage of the instruction-level parallelism (ILP) available in programs with advances in both architecture and compiler design. Unfortunately, large...