2784 search results - page 114 / 557 » Instruction Level Parallelism |
133
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WSC
2007
15 years 7 months ago
2007
The Cross-Entropy (CE) method is a modern and effective optimization method well suited to parallel implementations. There is a vast array of problems today, some of which are hig...
132
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FSEN
2007
Springer
15 years 11 months ago
2007
Springer
This paper shows how a machine-code Hoare logic is used to lift reasoning from the tedious operational model of a machine lana manageable level of abstraction without making simpli...
124
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APCSAC
2003
IEEE
15 years 10 months ago
2003
IEEE
The RAMpage hierarchy moves main memory up a level to replace the lowest-level cache by an equivalent-sized SRAM main memory, with a TLB caching page translations for that main mem...
145
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DATE
2002
IEEE
15 years 10 months ago
2002
IEEE
In this paper, we investigate the benefits of a flexible, application-specific instruction set by adding a run-time Reconfigurable Functional Unit (RFU) to a VLIW processor. Preli...
156
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HIPEAC
2007
Springer
15 years 8 months ago
2007
Springer
In this paper, we examine the trade-offs in performance and area due to customizing the datapath and instruction set architecture of a soft VLIW processor implemented in a high-den...