2784 search results - page 115 / 557 » Instruction Level Parallelism |
148
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CODES
2001
IEEE
15 years 8 months ago
2001
IEEE
"Function Tokens" and "NOP Fills" are two methods proposed by various authors to deal with Instruction Pointer corruption in microcontrollers, especially in th...
145
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LCTRTS
2000
Springer
15 years 8 months ago
2000
Springer
This paper presents a general approach to automatically validate code-improving transformations on low-level program representations. The approach ensures the correctness of compi...
110
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ICALT
2008
IEEE
15 years 11 months ago
2008
IEEE
This paper presents a task selection model for personalised educational instruction. The proposed model is based on the student expertise level and it takes into account performan...
133
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IPPS
2006
IEEE
15 years 11 months ago
2006
IEEE
The load/store queue (LSQ) is one of the most complex parts of contemporary processors. Its latency is critical for the processor performance and it is usually one of the processo...
154
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ICS
1999
Tsinghua U.
15 years 9 months ago
1999
Tsinghua U.
—This paper explores the use of compiler optimizations which optimize the layout of instructions in memory. The target is to enable the code to make better use of the underlying ...