2784 search results - page 116 / 557 » Instruction Level Parallelism |
149
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ICS
1999
Tsinghua U.
15 years 9 months ago
1999
Tsinghua U.
Instruction scheduling is an important compiler technique for exploiting more instruction-level parallelism (ILP) in high-performance microprocessors, and in this paper, we study ...
127
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IPPS
2000
IEEE
15 years 9 months ago
2000
IEEE
This paper presents a new methodology for implementing fast synchronization on scalable cache-coherent multiprocessors, through the use of hybrid primitives. Hybrid primitives lev...
154
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ASAP
2005
IEEE
15 years 10 months ago
2005
IEEE
We studied the dynamic instruction count reduction for a single-thread, vectorized and a multi-threaded, non-vectorized, MPEG-4 video encoder. Results indicate a maximum improveme...
147
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CW
2008
IEEE
15 years 11 months ago
2008
IEEE
Level set methods have been extensively used to track the dynamical interfaces between different materials for physically based simulation, geometry modeling, oceanic modeling and...
132
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ISSS
1998
IEEE
15 years 9 months ago
1998
IEEE
The concept of retargetability enables compiler technology to keep pace with the increasing variety of domain-speci c embedded processors. In order to achieve user retargetability,...