2784 search results - page 123 / 557 » Instruction Level Parallelism |
120
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HPCA
2005
IEEE
16 years 5 months ago
2005
IEEE
Long-latency loads are critical in today's processors due to the ever-increasing speed gap with memory. Not only do these loads block the execution of dependent instructions,...
159
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TCAD
2002
15 years 4 months ago
2002
In this paper, an instruction-level energy model is proposed for the data-path of very long instruction word (VLIW) pipelined processors that can be used to provide accurate power ...
126
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IPPS
2008
IEEE
15 years 11 months ago
2008
IEEE
We present an MPI topology discovery tool for homogeneous Ethernet switched clusters. Unlike existing Ethernet topology discovery methods that rely on Simple Network Management Pr...
133
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ESCIENCE
2007
IEEE
15 years 11 months ago
2007
IEEE
— SAGA is a high-level programming abstraction, which significantly facilitates the development and deployment of Grid-aware applications. The primary aim of this paper is to di...
160
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IPPS
2006
IEEE
15 years 11 months ago
2006
IEEE
Current electronic system design requires to be concerned with power consumption consideration. However, in a lot of design tools, the application power consumption budget is esti...