2784 search results - page 127 / 557 » Instruction Level Parallelism |
128
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ASPDAC
1998
ACM
15 years 9 months ago
1998
ACM
— The paper introduces a novel co-compiler and its “vertical” parallelization method, including a general model for co-operating host/accelerator platforms and a new parallel...
125
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HPCA
2004
IEEE
16 years 5 months ago
2004
IEEE
For highest performance, a modern microprocessor must be able to determine if an instruction is ready in the same cycle in which it is to be selected for execution. This creates a...
145
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HPCA
2004
IEEE
16 years 5 months ago
2004
IEEE
Data communications between producer instructions and consumer instructions through memory incur extra delays that degrade processor performance. In this paper, we introduce a new...
135
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IEEEPACT
2006
IEEE
15 years 11 months ago
2006
IEEE
In SMT processors, the complex interplay between private and shared datapath resources needs to be considered in order to realize the full performance potential. In this paper, we...
131
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IEEEPACT
2005
IEEE
15 years 10 months ago
2005
IEEE
This paper proposes a new hardware technique for using one core of a CMP to prefetch data for a thread running on another core. Our approach simply executes a copy of all non-cont...