2784 search results - page 130 / 557 » Instruction Level Parallelism |
187
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ESTIMEDIA
2009
Springer
15 years 11 months ago
2009
Springer
—Real-time encoding of high-definition H.264 video is a challenge to current embedded programmable processors. Emerging stream processing methods supported by most GPUs and progr...
122
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LCPC
2001
Springer
15 years 9 months ago
2001
Springer
Abstract. We describe the structure of a compilation system that generates code for processor architectures supporting both explicit and implicit parallel threads. Such architectur...
159
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PPOPP
2010
ACM
16 years 2 months ago
2010
ACM
Loop vectorization, a key feature exploited to obtain high performance on Single Instruction Multiple Data (SIMD) vector architectures, is significantly hindered by irregular memo...
143
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IPPS
2003
IEEE
15 years 10 months ago
2003
IEEE
The Adaptive Parallelism Environment is introduced as a means of effectively utilizing MPP processing resources in a multi-programmed MIMD or distributed system. It achieves this...
121
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ISCA
1992
IEEE
15 years 9 months ago
1992
IEEE
This paper discusses three techniques useful in relaxing the constraints imposed by control flow on parallelism: control dependence analysis, executing multiple flows of control s...