2784 search results - page 132 / 557 » Instruction Level Parallelism |
177
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MICRO
1999
IEEE
15 years 9 months ago
1999
IEEE
Current microprocessors incorporate techniques to exploit instruction-level parallelism (ILP). However, previous work has shown that these ILP techniques are less effective in rem...
145
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MICRO
2006
IEEE
15 years 4 months ago
2006
IEEE
We examine the ability of CMPs, due to their lower onchip communication latencies, to exploit data parallelism at inner-loop granularities similar to that commonly targeted by vec...
125
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VLSID
2009
IEEE
16 years 5 months ago
2009
IEEE
Code compression is important in embedded systems design since it reduces the code size (memory requirement) and thereby improves overall area, power and performance. Existing res...
154
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ISCA
1998
IEEE
15 years 9 months ago
1998
IEEE
This paper examines simultaneous multithreading, a technique permitting several independent threads to issue instructions to a superscalar's multiple functional units in a si...
112
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IISWC
2006
IEEE
15 years 10 months ago
2006
IEEE
—The rapid pace of change in 3D game technology makes workload characterization necessary for every game generation. Comparing to CPU characterization, far less quantitative info...