2784 search results - page 13 / 557 » Instruction Level Parallelism |
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MICRO
2007
IEEE
15 years 6 months ago
2007
IEEE
Recently, the microprocessor industry has moved toward chip multiprocessor (CMP) designs as a means of utilizing the increasing transistor counts in the face of physical and micro...
ISCA
1999
IEEE
15 years 4 months ago
1999
IEEE
Value Prediction is a relatively new technique to increase instruction-level parallelism by breaking true data dependence chains. A value prediction architecture produces values, ...
94
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PDPTA
2000
15 years 1 months ago
2000
Abstract In this paper, we propose a microprocessor architecture which eciently utilizes nextgeneration semiconductor technology. While the technology makes it possible to integrat...
MICRO
2005
IEEE
15 years 5 months ago
2005
IEEE
An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditiona...
VLSID
2004
IEEE
16 years 3 days ago
2004
IEEE
With increasing demands for high performance by embedded systems, especially by digital signal processing applications, embedded processors must increase available instruction lev...