2784 search results - page 141 / 557 » Instruction Level Parallelism |
154
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HPCA
2000
IEEE
15 years 9 months ago
2000
IEEE
Main memory accesses continue to be a significant bottleneck for applications whose working sets do not fit in second-level caches. With the trend of greater associativity in seco...
122
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ICPP
1993
IEEE
15 years 9 months ago
1993
IEEE
:. In designing application-specific bit-level architectures and in programming existing bit-level processor arrays, it is necessary to expand a word-level algorithm into its bit-...
144
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ISCA
1998
IEEE
15 years 8 months ago
1998
IEEE
Future parallel computers must efficiently execute not only hand-coded applications but also programs written in high-level, parallel programming languages. Today's machines ...
145
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ICCS
2004
Springer
15 years 10 months ago
2004
Springer
This paper presents a two-leveled mobile agent system for electronic commerce. It is based on mobile agents as mediators and uses the publish/subscribe paradigm for registration an...
148
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RULEML
2009
Springer
15 years 11 months ago
2009
Springer
Abstract. In this paper, a novel architecture for high-level scene interpretation is introduced, which is based on the generation of rules from an OWL-DL ontology. It is shown that...