2784 search results - page 150 / 557 » Instruction Level Parallelism |
187
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CGF
2011
14 years 8 months ago
2011
We investigate the use of two-level nested grids as acceleration structure for ray tracing of dynamic scenes. We propose a massively parallel, sort-based construction algorithm an...
138
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VLSID
2004
IEEE
16 years 5 months ago
2004
IEEE
The design of any application on a configurable System-on-a-Chip (SoC) like Atmel's FPSLIC is subject to a lot of constraints stemming from requirements of the application an...
116
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ISLPED
2003
ACM
15 years 10 months ago
2003
ACM
Many of the recently proposed techniques to reduce power consumption in caches introduce an additional level of nondeterminism in cache access latency. Due to this additional late...
193
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CC
2008
Springer
15 years 6 months ago
2008
Springer
JIT compilation is a model of execution which translates at run time critical parts of the program to a low level representation. Typically a JIT compiler produces machine code fro...
148
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MASCOTS
1994
15 years 6 months ago
1994
We investigate the feasibility of using instruction compression at some level in a multi-level memory hierarchy to increase memory system performance. Compression e ectively incre...