2784 search results - page 159 / 557 » Instruction Level Parallelism |
145
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IPPS
1998
IEEE
15 years 9 months ago
1998
IEEE
This paper shows the power of randomization in designing e cient parallel algorithms for the problems of routing and PRAM emulation. We show that with randomization techniques opti...
137
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ICCD
2003
IEEE
16 years 1 months ago
2003
IEEE
Modern processors rely heavily on broadcast networks to bypass instruction results to dependent instructions in the pipeline. However, as clock rates increase, architectures get w...
149
Voted
ISSS
1999
IEEE
15 years 9 months ago
1999
IEEE
Decreasing the program size has become an important goal in the design of embedded systems target to mass production. This problem has led to a number of efforts aimed at designin...
146
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EUROPAR
2009
Springer
15 years 11 months ago
2009
Springer
An upgrade from dual-core to quad-core AMD processor on the Cray XT system at the Oak Ridge National Laboratory (ORNL) Leadership Computing Facility (LCF) has resulted in significa...
114
Voted
ICPP
2006
IEEE
15 years 10 months ago
2006
IEEE
We propose a series of aggressive register deallocation mechanisms to reduce the register file pressure and increase the parallelism exploited by superscalar microprocessors. Our ...