2784 search results - page 161 / 557 » Instruction Level Parallelism |
139
Voted
ISCA
2008
IEEE
15 years 11 months ago
2008
IEEE
The current trend is for processors to deliver dramatic improvements in parallel performance while only modestly improving serial performance. Parallel performance is harvested th...
137
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HPCA
2006
IEEE
16 years 5 months ago
2006
IEEE
In high-end processors, increasing the number of in-flight instructions can improve performance by overlapping useful processing with long-latency accesses to the main memory. Buf...
127
Voted
HPCA
2004
IEEE
16 years 5 months ago
2004
IEEE
Branch misprediction penalty consists of two components: the time wasted on mis-speculative execution until the mispredicted branch is resolved and the time to restart the pipelin...
141
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CASES
2003
ACM
15 years 10 months ago
2003
ACM
Code size has always been an important issue for all embedded applications as well as larger systems. Code compression techniques have been devised as a way of battling bloated co...
134
Voted
HPCA
2002
IEEE
15 years 9 months ago
2002
IEEE
As the frequency gap between main memory and modern microprocessor grows, the implementation and efficiency of on-chip caches become more important. The growing latency to memory ...