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» Instruction Level Parallelism
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147
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MICRO
1999
IEEE
109views Hardware» more  MICRO 1999»
15 years 9 months ago
Compiler-Directed Dynamic Computation Reuse: Rationale and Initial Results
Recent studies on value locality reveal that many instructions are frequently executed with a small variety of inputs. This paper proposes an approach that integrates architecture...
Daniel A. Connors, Wen-mei W. Hwu
ASAP
2000
IEEE
102views Hardware» more  ASAP 2000»
15 years 8 months ago
A Theory for Software-Hardware Co-Scheduling for ASIPs and Embedded Processors
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded proces...
Ramaswamy Govindarajan, Erik R. Altman, Guang R. G...
143
Voted
ICCV
2003
IEEE
15 years 10 months ago
Unsupervised Non-parametric Region Segmentation Using Level Sets
We present a novel non-parametric unsupervised segmentation algorithm based on Region Competition [21]; but implemented within a Level Sets framework [11]. The key novelty of the ...
Timor Kadir, Michael Brady
156
Voted
PPOPP
2011
ACM
14 years 7 months ago
OoOJava: software out-of-order execution
Developing parallel software using current tools can be challenging. Even experts find it difficult to reason about the use of locks and often accidentally introduce race condit...
James Christopher Jenista, Yong Hun Eom, Brian Dem...
EUROMICRO
1999
IEEE
15 years 9 months ago
Software Synthesis for System Level Design Using Process Execution Trees
Software synthesis for system level design languages becomes feasible because the current technology, pricing and application trends will most likely alleviate the industrial empha...
Leo J. van Bokhoven, Jeroen Voeten, Marc Geilen