2784 search results - page 167 / 557 » Instruction Level Parallelism |
171
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ASPLOS
2004
ACM
15 years 10 months ago
2004
ACM
Increased integration in the form of multiple processor cores on a single die, relatively constant die sizes, shrinking power envelopes, and emerging applications create a new cha...
124
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HPCA
2008
IEEE
16 years 5 months ago
2008
IEEE
Fetch gating mechanisms have been proposed to gate the processor pipeline to reduce the wasted energy consumption due to wrongpath (i.e. mis-speculated) instructions. These scheme...
135
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ASAP
2003
IEEE
15 years 10 months ago
2003
IEEE
Symmetric-key block ciphers encrypt data, providing data confidentiality over the public Internet. For inter-operability reasons, it is desirable to support a variety of symmetric...
142
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MICRO
2003
IEEE
15 years 10 months ago
2003
IEEE
Silicon technology will continue to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, how...
113
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PDCN
2004
15 years 6 months ago
2004
This paper proposes a selective procedure inlining scheme to improve a multi-grain parallelism, which hierarchically exploits the coarse grain task parallelism among loops, subrou...