Sciweavers

2784 search results - page 169 / 557
» Instruction Level Parallelism
Sort
View
HPCA
1996
IEEE
15 years 8 months ago
Co-Scheduling Hardware and Software Pipelines
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded process...
Ramaswamy Govindarajan, Erik R. Altman, Guang R. G...
MICRO
1991
IEEE
115views Hardware» more  MICRO 1991»
15 years 8 months ago
Executing Loops on a Fine-Grained MIMD Architecture
- We present techniques for exploiting parallelism extracted from loops on an MIMD system. Parallelism is exploited through parallel execution of instructions on multiple processor...
Sunah Lee, Rajiv Gupta
PDPTA
2007
15 years 6 months ago
Suppressing Independent Loops in Packing/Unpacking Loop Nest to Reduce Message Size for Message-passing Code
- In this paper we experiment with two optimization techniques we are considering implementing in a parallelizing compiler that generates parallel code for a distributed-memory sys...
P. Jerry Martin, Clayton S. Ferner
IPPS
1996
IEEE
15 years 8 months ago
A Hierarchical Parallel Processing System for the Multipass-Rendering Method
The multipass-rendering method integrating radiosity with ray-tracing gives one of the best solutions for synthesizing photo-realistic images. However, the method is also computat...
Hiroaki Kobayashi, Hitoshi Yamauchi, Yuichiro Toh,...
EDCC
2006
Springer
15 years 8 months ago
SEU Mitigation Techniques for Microprocessor Control Logic
The importance of fault tolerance at the processor architecture level has been made increasingly important due to rapid advancements in the design and usage of high performance de...
T. S. Ganesh, Viswanathan Subramanian, Arun K. Som...