2784 search results - page 170 / 557 » Instruction Level Parallelism |
148
click to vote
HPCA
2001
IEEE
16 years 4 months ago
2001
IEEE
Mispredicted branches and loads that miss in the cache cause the majority of retirement stalls experienced by sequential processors; we call these critical instructions. Despite t...
127
click to vote
IEEEPACT
2000
IEEE
15 years 9 months ago
2000
IEEE
In this paper, we look at two issues which could affect the performance of value prediction on wide-issue ILP processors. One is the large number of accesses to the value predicti...
152
Voted
ICPP
2007
IEEE
15 years 11 months ago
2007
IEEE
This paper presents COBRA (Continuous Binary ReAdaptation), a runtime binary optimization framework, for multithreaded applications. It is currently implemented on Itanium 2 based...
152
Voted
MVA
1992
15 years 5 months ago
1992
In this work the Low Level Vision Unit (LLVU) of the Heterogeneous and Reconfigurable Machine for Image Analysis (HERMIA) is described. The LLVU consists of the innovative integra...
130
click to vote
DAGSTUHL
1997
15 years 5 months ago
1997
This paper describes and demonstrates the e ectiveness of several metrics for data level comparison of direct volume rendering (DVR) algorithms. The focus is not on speed ups from...