2784 search results - page 193 / 557 » Instruction Level Parallelism |
122
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ICCD
2001
IEEE
16 years 1 months ago
2001
IEEE
The general-purpose precise interrupt mechanism, which has long been used to handle exceptional conditions that occur infrequently, is now being used increasingly often to handle ...
125
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IEEEPACT
2009
IEEE
15 years 11 months ago
2009
IEEE
—CPR (Checkpoint Processing and Recovery) is a physical register management scheme that supports a larger instruction window and higher average IPC than conventional ROB-style re...
171
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ICS
2007
Tsinghua U.
15 years 10 months ago
2007
Tsinghua U.
Software or hardware data cache prefetching is an efficient way to hide cache miss latency. However effectiveness of the issued prefetches have to be monitored in order to maximi...
152
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ACRI
2006
Springer
15 years 10 months ago
2006
Springer
For simulating physical and chemical processes on molecular level asynchronous cellular automata with probabilistic transition rules are widely used being sometimes referred to as ...
139
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ISMS
2004
Springer
15 years 9 months ago
2004
Springer
Physically based modeling of deformable objects such as cloth or human tissue has grown to be very important for virtual simulations. However, interactive simulation of these nonl...